1. Field of the Invention
The invention lies in the field of memory devices and pertains, more specifically, to a read/write memory which has one ferroelectric capacitor and at least one transistor per memory cell. In ferroelectric memories, the remanence of the electric polarization of the dielectric is used to store two logic states. When this is done, different effects occur which influence the polarization of other cells on the same bit or word line. It is thereby possible that the stored information of those cells is destroyed. If there are no fixed potentials present in a polarized capacitor, due to leakage current to the substrate, a voltage builds up which is possibly in the opposite direction to the polarization. It is therefore necessary to keep both sides of the capacitor as far as possible at the same potential if that capacitor has not been read out or written to.
The Digest of Technical Papers from the Symposium on VLSI Circuits 1997, pages 83 and 84, discloses a ferroelectric memory in which a plurality of memory cells or ferroelectric capacitors are connected in series and the respective capacitors can be short-circuited by one associated transistor each. This ensures that both the electrodes of a ferroelectric capacitor are kept at the same potential which, if not read or written to, is even constant. If a cell is written to or read, the corresponding transistor is switched off. In addition, the bit line has applied to it a voltage which differs significantly from the voltage on the capacitor plate which cannot be connected to the bit line. The difference between the two voltages has the effect of charging to saturation the ferroelectric capacitor. All other transistors in a respective series circuit composed of memory cells and/or in a respectively selected memory cell block remain conductive during this time, ensuring that the charge current or discharge current across the selected cell capacitor can flow via the transistors which are short-circuiting the remaining capacitors of a memory cell block. However, a voltage which is also applied to the associated ferroelectric capacitor, and which favors or attenuates polarization depending on the polarization of the ferroelectric capacitor and according to the direction of the charge current or discharge current drops as a result of the on resistance of the switched-on transistors. In the case of attenuation, those voltage drops are manifest as interference pulses which, given sufficient amplitude and/or frequency, change the polarization to such an extent that the stored information of the ferroelectric capacitor is destroyed. A series circuit comprised of the greatest possible number of such ferroelectric memory cells increases the overall resistance of the current path and reduces the level of the current, as a result of which the undesired interference pulses at the ferroelectric capacitors of the non-selected memory cells are also reduced. However, this has the disadvantage that the charging and discharging process of the ferroelectric capacitor which is being read and written to is significantly prolonged. For this reason, in the prior art disclosed above, a plurality of memory cell blocks, with series circuits composed of, for example, 16 individual cells, are provided. The disadvantage there is that the interference pulses are often unacceptably high and a data loss occurs because the on resistance of the transistors cannot be reduced as desired owing to the very large transistor width or very high charge carrier mobility which this requires.
The object of the present invention is to provide a ferroelectric read/write memory which has memory cells connected in series and which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this general kind, and in which both interference voltages at ferroelectric capacitors of non-selected memories and the expenditure in terms of circuitry are kept as low as possible.
With the above and other objects in view there is provided, in accordance with the invention, a ferroelectric read/write memory with a plurality of memory cells connected in series:
the memory cells have a respective ferroelectric capacitor, a respective resistor, and a transistor with a gate connected to a word line;
the resistor and the ferroelectric capacitor of a memory cell are connected in series forming a series circuit; and
the transistor is connected in parallel with the series circuit containing the ferroelectric capacitor and the resistor and is driven via a signal on the word line connected to its gate.
In accordance with an added feature of the invention, the resistor is replaced with a further transistor having a conductivity depending on the signal of the word line.
In accordance with a concomitant feature of the invention, a control unit is connected to the memory cells, the control unit switching on the further transistor in a memory cell selected via the signal of the respective word line as a function of the signal, and driving all other further transistors of the non-selected memory cells to just before their switch-off threshold.
In other words, according to the invention, the series circuit containing the ferroelectric capacitor and the resistor are connectible in low-impedance fashion via the respective transistor as a function of a signal of a respective word line connected to the gate of the respective the transistor.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a ferroelectric read/write memory with memory cells (CFRAM) connected in series., it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.